From 3dcea0e86e4f4982102ff72e01e5e705d0521848 Mon Sep 17 00:00:00 2001
From: 0xllx0 <github+elle@weathered-steel.dev>
Date: Wed, 10 Sep 2025 23:54:51 +0000
Subject: [PATCH 1/2] register: add `miselect` CSR

Adds the `miselect` register for selecting an indirect CSR according to
the `Smcsrind` extension.

Reference:

<https://riscv-software-src.github.io/riscv-unified-db/manual/html/isa/isa_20240411/chapters/indirect-csr.html>
---
 riscv/src/register.rs          |  3 +++
 riscv/src/register/miselect.rs | 47 ++++++++++++++++++++++++++++++++++
 2 files changed, 50 insertions(+)
 create mode 100644 riscv/src/register/miselect.rs

diff --git a/riscv/src/register.rs b/riscv/src/register.rs
index cabd1922..2dc9f534 100644
--- a/riscv/src/register.rs
+++ b/riscv/src/register.rs
@@ -117,6 +117,9 @@ pub mod mseccfg;
 #[cfg(any(test, target_arch = "riscv32"))]
 pub mod mseccfgh;
 
+// Machine indirect access
+pub mod miselect;
+
 #[cfg(test)]
 mod tests;
 
diff --git a/riscv/src/register/miselect.rs b/riscv/src/register/miselect.rs
new file mode 100644
index 00000000..abdd3341
--- /dev/null
+++ b/riscv/src/register/miselect.rs
@@ -0,0 +1,47 @@
+//! `miselect` register.
+
+const MASK: usize = usize::MAX;
+
+read_write_csr! {
+    /// `miselect` register.
+    Miselect: 0x350,
+    mask: MASK,
+}
+
+#[cfg(target_arch = "riscv32")]
+read_write_csr_field! {
+    Miselect,
+    /// Returns whether `miselect` is for custom use of indirect CSRs.
+    is_custom: 31,
+}
+
+#[cfg(not(target_arch = "riscv32"))]
+read_write_csr_field! {
+    Miselect,
+    /// Returns whether `miselect` is for custom use of indirect CSRs.
+    is_custom: 63,
+}
+
+#[cfg(target_arch = "riscv32")]
+read_write_csr_field! {
+    Miselect,
+    /// Gets the value stored in the `miselect` CSR.
+    ///
+    /// # Note
+    ///
+    /// The semantics of the value depend on the extension for the referenced CSR,
+    /// and the relevant `mireg*` value.
+    value: [0:30],
+}
+
+#[cfg(not(target_arch = "riscv32"))]
+read_write_csr_field! {
+    Miselect,
+    /// Gets the value stored in the `miselect` CSR.
+    ///
+    /// # Note
+    ///
+    /// The semantics of the value depend on the extension for the referenced CSR,
+    /// and the relevant `mireg*` value.
+    value: [0:62],
+}

From b4385d05642536ccb652377b4ef6ca6d0d86087a Mon Sep 17 00:00:00 2001
From: 0xllx0 <github+elle@weathered-steel.dev>
Date: Fri, 12 Sep 2025 00:32:31 +0000
Subject: [PATCH 2/2] test: add unit test for `miselect`

Adds a basic unit test for the `miselect` CSR.
---
 riscv/CHANGELOG.md             |  4 ++++
 riscv/src/register/miselect.rs | 17 +++++++++++++++++
 2 files changed, 21 insertions(+)

diff --git a/riscv/CHANGELOG.md b/riscv/CHANGELOG.md
index 59dc1adb..a405c5ad 100644
--- a/riscv/CHANGELOG.md
+++ b/riscv/CHANGELOG.md
@@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Added
+
+- Add `miselect` CSR
+
 ## [v0.15.0] - 2025-09-08
 
 ### Added
diff --git a/riscv/src/register/miselect.rs b/riscv/src/register/miselect.rs
index abdd3341..50aa624f 100644
--- a/riscv/src/register/miselect.rs
+++ b/riscv/src/register/miselect.rs
@@ -45,3 +45,20 @@ read_write_csr_field! {
     /// and the relevant `mireg*` value.
     value: [0:62],
 }
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test() {
+        (0..=usize::BITS)
+            .map(|r| ((1u128 << r) - 1) as usize)
+            .for_each(|bits| {
+                let mut miselect = Miselect::from_bits(bits);
+
+                test_csr_field!(miselect, is_custom);
+                test_csr_field!(miselect, value: [0, usize::BITS - 2], 0);
+            });
+    }
+}