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AxC1271/README.md

Hi, I'm Andrew!

πŸ’» Computer Engineer Documenting my Projects/Learning
πŸ§‘β€πŸŽ“ Undergraduate Student at Case Western Reserve University
βš™οΈ Currently learning about VLSI Design (Digital and Analog)
πŸ“Ÿ Skilled in RTL scripting and FPGA toolchains

Hi! I am a Case undergraduate student studying computer engineering. My interests are coding, badminton, rock climbing, and baking! Outside of academics, you can catch me skateboarding around campus, playing chess, doodling, or sleeping. :)

πŸ’» Tech Stack:

TypeScript C Python Docker PlatformIO Raspberry Pi AMD nVIDIA

πŸ“Š GitHub Stats:



πŸ” Top Contributed Repo

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  1. MetaStable MetaStable Public

    This GitHub repository explores the concept of clock domain crossing using different techniques. The deliverable is not some hardware but rather an educational source for such techniques. Often use…

    1

  2. StenoKey StenoKey Public

    This is a personal project documenting the design process of a custom made mechanical stenography keyboard on KiCAD, from schematic to complete PCB.

    1

  3. STM32-DevBoard STM32-DevBoard Public

    This is my personal project on using KiCad 7.0 to design, build, and manufacture a simple STM32 development board. Later, the board will be interfaced with a UART receiver on my FPGA board.

    Verilog 1

  4. RISCV-CPU RISCV-CPU Public

    This is a RTL approach to implementing a simple RISC-V processor using VHDL and the Basys3 FPGA board.

    VHDL 1