Fix cache invalidation for SPI transfer

[josesimoes]

Description

• Calculation of buffer length is now correct for 16 bits transfer in ChibiOS.

Motivation and Context

How Has This Been Tested?

• Running test application that uses 16 bits transfer.

Screenshots

Types of changes

• Improvement (non-breaking change that improves a feature, code or algorithm)
• Bug fix (non-breaking change which fixes an issue with code or algorithm)
• New feature (non-breaking change which adds functionality to code)
• Breaking change (fix or feature that would cause existing functionality to change)
• Config and build (change in the configuration and build system, has no impact on code or features)
• Dev Containers (changes related with Dev Containers, has no impact on code or features)
• Dependencies/declarations (update dependencies or assembly declarations and changes associated, has no impact on code or features)
• Documentation (changes or updates in the documentation, has no impact on code or features)

Checklist

• My code follows the code style of this project (only if there are changes in source code).
• My changes require an update to the documentation (there are changes that require the docs website to be updated).
• I have updated the documentation accordingly (the changes require an update on the docs in this repo).
• I have read the CONTRIBUTING document.
• I have tested everything locally and all new and existing tests passed (only if there are changes in source code).

Summary by CodeRabbit

• Chores
  • Improved variable naming for clarity and consistency.
  • Enhanced readability of the code structure without changing functionality.

[coderabbitai]

Walkthrough

The changes involve modifications to the CompleteTranfer function in the cpu_spi.cpp file. The variable ReadSize has been renamed to readSize for consistency, and the read size adjustment for 16-bit data width has been enclosed in braces for improved readability. The cache buffer invalidation calculation now uses the renamed variable, maintaining the original logic while adhering to the new naming convention.

Changes

Files	Change Summary
targets/ChibiOS/_nanoCLR/System.Device.Spi/cpu_spi.cpp	Renamed ReadSize to readSize, adjusted read size logic for 16-bit data width, and updated cache buffer invalidation calculation.

Possibly related PRs

• Fix SPI CS handling #3010: The changes in this PR involve modifications to the cpu_spi.cpp file, specifically in the CPU_SPI_nWrite_nRead function, which is directly related to the SPI functionality being modified in the main PR's CompleteTranfer function.

Suggested labels

Area: Common libs

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Recent review details

Configuration used: CodeRabbit UI
Review profile: CHILL

Commits

Files that changed from the base of the PR and between 0223857 and c23da1e.

Files selected for processing (1)

• targets/ChibiOS/_nanoCLR/System.Device.Spi/cpu_spi.cpp (1 hunks)

Files skipped from review due to trivial changes (1)

• targets/ChibiOS/_nanoCLR/System.Device.Spi/cpu_spi.cpp

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