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@riscv-software-src

RISC-V Software

The Open-Standard Instruction Set Architecture
README.md

Welcome to the RISC-V Software Repos 👋

RISC-V Logo

These repos consist of RISC-V software that is maintained by RISC-V International. These repositories represent upstream sources for many open source projects.

Things you'll find here include:

  • Spike, a RISC-V Simulator
  • riscof, the RISC-V Architectural Test Framework
  • opensbi, a RISC-V Supervisor Binary Interface reference implementation

If you don't find what you're looking for here, try one of our other GitHub organizations:

Popular repositories Loading

  1. riscv-isa-sim riscv-isa-sim Public

    Spike, a RISC-V ISA Simulator

    C 2.8k 974

  2. opensbi opensbi Public

    RISC-V Open Source Supervisor Binary Interface

    C 1.3k 605

  3. riscv-tools riscv-tools Public archive

    RISC-V Tools (ISA Simulator and Tests)

    Shell 1.2k 449

  4. riscv-tests riscv-tests Public

    C 1.1k 514

  5. riscv-pk riscv-pk Public

    RISC-V Proxy Kernel

    C 659 330

  6. homebrew-riscv homebrew-riscv Public

    homebrew (macOS) packages for RISC-V toolchain

    Ruby 351 55

Repositories

Showing 10 of 24 repositories
  • riscv-unified-db Public

    Monorepo containing a machine-readable database of the RISC-V specification and artifact generation tools

    riscv-software-src/riscv-unified-db’s past year of commit activity
    C++ 102 BSD-2-Clause 69 164 (1 issue needs help) 57 Updated Sep 10, 2025
  • riscv-isa-sim Public

    Spike, a RISC-V ISA Simulator

    riscv-software-src/riscv-isa-sim’s past year of commit activity
    C 2,822 974 305 49 Updated Sep 9, 2025
  • riscv-mirror-mavis Public

    Mirror of Mavis. Mavis is a framework that allows decoding of the RISC-V ISA into custom instruction class types as well as custom extensions to those class types.

    riscv-software-src/riscv-mirror-mavis’s past year of commit activity
    C++ 0 Apache-2.0 0 0 0 Updated Sep 6, 2025
  • riscv-perf-model Public

    Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model

    riscv-software-src/riscv-perf-model’s past year of commit activity
    C++ 187 Apache-2.0 75 32 2 Updated Sep 4, 2025
  • sail-riscv-tests Public

    Precompiled test suites for comprehensive testing of the Sail RISC-V model

    riscv-software-src/sail-riscv-tests’s past year of commit activity
    1 Apache-2.0 1 1 1 Updated Sep 1, 2025
  • opensbi Public

    RISC-V Open Source Supervisor Binary Interface

    riscv-software-src/opensbi’s past year of commit activity
    C 1,252 605 83 3 Updated Sep 1, 2025
  • riscof Public
    riscv-software-src/riscof’s past year of commit activity
    Python 90 BSD-3-Clause 47 57 (4 issues need help) 15 Updated Aug 29, 2025
  • riscv-mirror-stf-library Public

    Mirror of STF Library. The acronym STF stands for Simulation Trace Format. This is intended to be used with Sparta-based simulators, but that's not necessary.

    riscv-software-src/riscv-mirror-stf-library’s past year of commit activity
    C++ 0 Apache-2.0 0 0 0 Updated Aug 26, 2025
  • homebrew-riscv Public

    homebrew (macOS) packages for RISC-V toolchain

    riscv-software-src/homebrew-riscv’s past year of commit activity
    Ruby 351 55 3 2 Updated Aug 17, 2025
  • librpmi Public

    Reference implementation of RPMI specification as a library.

    riscv-software-src/librpmi’s past year of commit activity
    C 11 13 3 1 Updated Aug 14, 2025
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risc-v riscv