riscv: add the miselect CSR

riscv/CHANGELOG.md

@@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Added
+
+- Add `miselect` CSR
+
 ## [v0.15.0] - 2025-09-08
 
 ### Added

riscv/src/register.rs

@@ -117,6 +117,9 @@ pub mod mseccfg;
 #[cfg(any(test, target_arch = "riscv32"))]
 pub mod mseccfgh;
 
+// Machine indirect access
+pub mod miselect;
+
 #[cfg(test)]
 mod tests;
 

riscv/src/register/miselect.rs

@@ -0,0 +1,64 @@
+//! `miselect` register.
+
+const MASK: usize = usize::MAX;
+
+read_write_csr! {
+    /// `miselect` register.
+    Miselect: 0x350,
+    mask: MASK,
+}
+
+#[cfg(target_arch = "riscv32")]
+read_write_csr_field! {
+    Miselect,
+    /// Returns whether `miselect` is for custom use of indirect CSRs.
+    is_custom: 31,
+}
+
+#[cfg(not(target_arch = "riscv32"))]
+read_write_csr_field! {
+    Miselect,
+    /// Returns whether `miselect` is for custom use of indirect CSRs.
+    is_custom: 63,
+}
+
+#[cfg(target_arch = "riscv32")]
+read_write_csr_field! {
+    Miselect,
+    /// Gets the value stored in the `miselect` CSR.
+    ///
+    /// # Note
+    ///
+    /// The semantics of the value depend on the extension for the referenced CSR,
+    /// and the relevant `mireg*` value.
+    value: [0:30],
+}
+
+#[cfg(not(target_arch = "riscv32"))]
+read_write_csr_field! {
+    Miselect,
+    /// Gets the value stored in the `miselect` CSR.
+    ///
+    /// # Note
+    ///
+    /// The semantics of the value depend on the extension for the referenced CSR,
+    /// and the relevant `mireg*` value.
+    value: [0:62],
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test() {
+        (0..=usize::BITS)
+            .map(|r| ((1u128 << r) - 1) as usize)
+            .for_each(|bits| {
+                let mut miselect = Miselect::from_bits(bits);
+
+                test_csr_field!(miselect, is_custom);
+                test_csr_field!(miselect, value: [0, usize::BITS - 2], 0);
+            });
+    }
+}